The present invention relates generally to memory devices, and more particularly to cache memories. A cache memory is a random access memory that buffers data from a main memory. A cache memory is typically employed to provide high bandwidth memory accessing to a processor. Typically, such a cache memory reflects selected locations of the main memory. A typical memory contains a memory array organized into a set of cache blocks, often referred to as cache lines. A cache memory is usually smaller than the corresponding main memory. As a consequence, each cache line stored in the cache memory includes a corresponding address tag that identifies the main memory location for that cache line.
The increasing gap between memory and processor speeds continues to challenge computer architects. Enabled by increasing process densities, architects have responded to this challenge partly by dedicating an increasing portion of a processor's real estate to large caches, thereby increasing cache capacity. For example, the caches in modem microprocessors consume over half of the total chip real estate. However, leakage current in large data arrays increases power consumption and pushes power envelopes. These factors therefore limit cache sizes, which require more accesses to main memory, and thus increase bottlenecks in processor operation.
A need thus exists for improved caching mechanisms.